Cerebras Doubles Down on Power Density with WSE-3T and CS-4
AI-generated image · US National Wire
The chipmaker is pushing existing silicon to its limits, doubling performance through increased clock speeds and a new modular rack architecture.
Cerebras has unveiled the WSE-3T accelerator and the CS-4 rack system, focusing on boosting throughput per watt tenfold over the previous generation, as first reported by The Register.
The WSE-3T, dubbed the "Turbo" variant, does not utilize new silicon. Instead, Cerebras is pushing the existing WSE-3 wafer scale engine harder by increasing operating frequencies. The Register estimates the silicon now clocks at 2.8 GHz, up from 1.4 GHz. This results in doubled compute, memory fabric, and I/O bandwidth, with the WSE-3T delivering 250 petaFLOPS of sparse FP16 AI compute and 43.2 PB/s of memory bandwidth.
This performance jump comes with a significant increase in power requirements. The Register reports that the estimated wafer-level TDP has risen from 15 kW for the WSE-3 to 33 kW for the WSE-3T, while the estimated system TDP has increased from 23 kW to 46 kW. Cerebras attributes these gains to more efficient power delivery that allows twice as many watts to be pushed through the chip.
To support this density, Cerebras is moving to a modular rack-scale architecture with the CS-4. The system utilizes a "backpack" form factor for the accelerators, allowing up to three backpacks to be plugged into the rear of the rack, while the front is dedicated to power shelves.
Cerebras is also shifting its deployment strategy. Rather than running the full inference stack alone, the company has partnered with AMD and Amazon Web Services (AWS) to offload prompt processing to Instinct GPUs and Trainium XPUs, respectively, allowing Cerebras chips to function primarily as decode accelerators.