AMD Revives Epyc X-Series with Venice-X Architecture
AI-generated image · US National Wire
New cache-heavy chips targeting EDA and HPC workloads are slated for a 2027 release.
AMD is bringing back its cache-packed Epyc X-series processors after a three-year gap, according to reporting from The Register. The upcoming Venice-X parts are designed specifically for high-performance computing (HPC) and electronic design automation (EDA) workloads, such as computational fluid dynamics and functional verification testing.
To address latency-sensitive tasks, the Venice-X will utilize 3D V-Cache chip stack technology to triple L3 cache density to over one gigabyte. AMD Fellow Phil Steinke explained to The Register that increasing the cache allows more of the model to remain on-chip, reducing the time CPU cores spend waiting for data to transfer from system memory. The new hardware will offer up to 96 cores.
While AMD previously deployed this SRAM stacking technology in the 2022 Ryzen 7 5800X3D and subsequent Milan-generation Epycs, the company omitted a "Turin-X" variant from its fifth-generation Epyc roadmap in late 2024. The Register reports that the Venice-X is expected to begin shipping in the second half of 2027.