The CXL Gilded Cage: Samsung and XCENA’s Memory Play is a Proprietary Dead End

*(Opinion)*

I have seen this movie before. The script always starts with a 'bottleneck'—first it was the bus, then it was the memory wall, and now it is the insatiable appetite of machine learning models for capacity. The industry's current answer is CXL (Compute Express Link), and the latest iteration of this promise comes from a partnership between Samsung and XCENA.

On paper, the hardware is a beast. As first reported by Chips and Cheese, Samsung and XCENA have developed the MX1, a "Memory Xcelerator" device designed to expand memory while hosting its own compute. It is a PCIe add-in card that connects via a CXL 3.2 x8 interface, delivering 128 GB/s of total bandwidth to the host. The capacity is staggering: it can host up to 2 TB of DDR5 memory and includes eight downstream PCIe 6 lanes for SSD connectivity. By using the attached DRAM as a cache for SSD storage, the MX1 makes a massive amount of memory visible to the host.

But the real story isn't the capacity; it's the onboard compute. Chips and Cheese reports that the MX1 chip, fabricated on Samsung’s 4nm process, packs 3,072 RISC-V cores. These aren't high-performance monsters; they run at a "pedestrian" 1.1 GHz and use in-order execution. Instead, XCENA has bet on a massive array of small, power-efficient cores to handle data-parallel workloads—a strategy Chips and Cheese notes is reminiscent of Intel’s Xeon Phi.

Technically, the architecture is a fascinating exercise in efficiency. The cores are organized into clusters of 32, which are then grouped into 24 "subsystems" that serve as the smallest unit for job allocation. To keep the pipes full without melting the board, XCENA uses a GPU-like cache hierarchy. To minimize translation overhead, each core is equipped with a 4 KB virtually addressed L1 data cache, while L2 data caches of 128 KB are shared across clusters. On the instruction side, four cores share an 8 KB instruction cache, designed to contain kernel hot loops, while a 128 KB L2 instruction cache handles larger footprints.

XCENA has even pushed the extensibility of RISC-V by adding a custom Vector Processing Engine (VPE) at the subsystem level. As reported by Chips and Cheese, this VPE supports FP32 and FP16, delivering approximately 3 TFLOPS of dot product throughput across the chip. The programming model mirrors CUDA or OpenCL, where a single kernel is invoked multiple times, and the host and MX1 share pointers through virtual memory mappings.

Here is where the realism kicks in. Samsung is betting that by integrating compute directly into the memory expansion layer, they can solve the latency and bandwidth issues plaguing AI. But look at the structure: the MX1 is a proprietary piece of silicon, built on a proprietary process, designed to slot into a centralized server architecture.

We are being sold a solution to the memory bottleneck that actually reinforces the existing power structures. By moving the compute to the memory, Samsung and XCENA aren't decentralizing the workload; they are just moving the goalposts of where the proprietary hardware lives. Without a truly decentralized compute layer—one that isn't tethered to the legacy PCIe/CXL host-client relationship—the MX1 is just another expensive wall.

It is a brilliant piece of engineering, but it is engineering for the status quo. The MX1 consumes 40W on its own, and 90W when accounting for four DIMMs. It is a powerhouse of efficiency, but it remains a tool for the big players to consolidate their grip on the ML stack. If the goal is to democratize compute, putting 3,000 RISC-V cores on a Samsung-fabricated card that still answers to a central host isn't the revolution we were promised. It's just a faster way to run the same centralized machine.