The $2 Billion Bridge: Why Silicon Interposers Are the Real AI Bottleneck
AI-generated image · US National Wire
A new partnership between TSMC and GlobalFoundries targets a critical gap in US advanced packaging, but the timeline reveals a stark reality for domestic AI infrastructure.
In the rush to build out AI infrastructure, the industry often focuses on the logic of the chip or the scale of the funding. But as a pragmatic observer of deployment, I look at the physical bottlenecks. Right now, the most critical bottleneck for American semiconductor manufacturing isn't just the wafer—it's the advanced packaging.
As first reported by The Register, a significant hole in the domestic supply chain is being addressed via a $2 billion partnership between TSMC and GlobalFoundries. Under this multi-year agreement, GlobalFoundries will utilize its fab site in Malta, New York, to produce silicon interposers. These parts are essential for the chip-on-wafer-on-substrate (CoWoS) advanced packaging spec used by TSMC.
To understand why this matters, you have to understand the physics of the hardware. As The Register explains, silicon interposers are necessary for multi-die chip assemblies, including AI accelerators and GPUs. They sit beneath the memory and compute logic, enabling communication paths that are faster and more power-efficient than conventional organic packaging. Essentially, any chip utilizing high-bandwidth memory (HBM) today requires an interconnect bridge or interposer to function.
Without this capacity in the US, the 'domestic' nature of chip production is often an illusion. The Register notes that when TSMC began producing Nvidia's Blackwell GPUs at its Arizona plant last year, the products still had to be shipped to Taiwan and back for final assembly.
TSMC is attempting to solve this through multiple channels. The company has signed a deal with Amkor, an outsourced semiconductor assembly and test (OSAT) provider, to provide CoWoS compatible packaging within the US. Furthermore, TSMC has started construction on its own advanced packaging plants in Arizona. However, the timeline for these facilities is the real story: neither is expected to be operational until 2028 and 2029, respectively.
GlobalFoundries is also expanding capacity at its Malta plant to meet this demand, but The Register reports that volume production there will not start until the first half of 2028 at the earliest. This partnership is slated to last five years, with an option for extension.
While the TSMC-GlobalFoundries deal is a massive bet on the CoWoS standard, it isn't the only path forward. The Register points out that Intel Foundry already provides advanced packaging technology comparable to CoWoS, which is compatible with silicon produced at TSMC fabs. Intel already packages TSMC-made chips in its own facilities, though this requires customers to design their parts specifically for Intel's packaging.
For those betting on US AI dominance, the takeaway is clear: the slide decks promise immediate scaling, but the physical reality is a waiting game that extends well into 2028.

